The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. Because of the high-precision required in the production of these integrated circuits, an extremely flat surface is generally needed on at least one side of the semiconductor wafer to ensure proper accuracy and performance of the microelectronic structures being created on the wafer surface. As the size of the integrated circuits continues to decrease and the density of microstructures on an integrated circuit increases, the need for precise wafer surfaces becomes more important. Therefore, between each processing step, it is usually necessary to polish or planarize the surface of the wafer to obtain the flattest surface possible.
For a discussion of chemical mechanical planarization (CMP) processes and apparatus, see, for example, Arai, et al., U.S. Pat. No. 4,805,348, issued February, 1989; Arai, et al., U.S. Pat. No. 5,099,614, issued March, 1992; Karlsrud et al., U.S. Pat. No. 5,329,732, issued July, 1994; Karlsrud, U.S. Pat. No. 5,498,196, issued March, 1996; and Karlsrud et al., U.S. Pat. No. 5,498,199, issued March, 1996. One typical CMP procedure involves the removal of one or more semiconductor layers originally present on a wafer. The removal of these layers (often formed of metallic materials such as tungsten, titanium, or the like) eventually exposes the oxide layer of the wafer. The endpoint of such a removal procedure may be indicated by the exposure of the oxide layer, the elimination of the metallic layers, the thickness of the oxide layer, the thickness of the wafer, or other measurable parameters of the wafer.
Methods and systems for performing endpoint detection are disclosed in U.S. patent application Ser. No. 08/798,803, filed Feb. 12, 1997, now U.S. Pat. No. 5,872,633 and entitled Methods and Apparatus for Detecting Removal of Thin Film Layers During Planarization, and U.S. patent application Ser. No. 08/687,710, filed Jul. 26, 1996, now abandoned and entitled Methods and Apparatus for the In-process Measurement of Thin Film Layers, both of which are hereby incorporated by reference. The systems disclosed in these applications utilize an optical probe device that detects reflective characteristics of the semiconductor wafer surface during planarization. Unfortunately, water, slurries, and other processing materials present on the wafer surface and/or the optical probe may adversely affect the performance of such systems.
Previous attempts at cleaning the workpiece surfaces during such endpoint detection procedures have employed compressed air directed at the point where the optical interrogation signal contacts the workpiece surface. Unfortunately, the compressed air may dry the workpiece surface and/or the slurry, which can cause material build-up and scratching of the polished surface. Furthermore, the compressed air may blow loose particulate onto the surface of the workpiece; such particulate may damage the workpiece or alter the polishing characteristics of the slurry.